Commit 5e15ef31 authored by Jules Saget's avatar Jules Saget
Browse files

Finish v1!

parent 25594172
......@@ -117,7 +117,7 @@
\paragraph{Note:} This internship lead to the submission of two papers:
\cite{CEPHALOPODE} and \cite{stately}.
\cite{CEPHALOPODE} and \cite{stately}.
Some of the content of this report is directly taken from what I have written
for these papers.
When a part is mostly taken from one of these papers, the reader will be warned
......@@ -194,7 +194,7 @@ The main objective of the internship was to come up with basic implementations
of arithmetical operations, so that proving their correctness would be easier.
A secondary objective was to find out the tools we did not have (and therefore
should make) that could help us designing hardware, such as
Stately \cite{stately}.
\section{Tools and theory}
......@@ -244,7 +244,7 @@ Consider this $\lambda$-expression:
After compiling this to combinators using a standard “brackecting” approach
\cite{Pey87}, we would obtain the leftmost graph shown in figure
\cite{Pey87}, we would obtain the leftmost graph shown in figure
......@@ -258,7 +258,7 @@ Note that the reduction of \emph{I} is done before the application of $+$.
This is because addition is strict in its arguments: it will use them both, so
both of them needs to be reduced.
The way we handled the order of the reductions is descibed in
\subsection{Low-level data representation}
......@@ -367,7 +367,7 @@ and, most importantly, a system wide issue rather than an arithmetic issue.
To motivate our representation, consider how numbers are represented
with various numbers of bits, as shown in Table~\ref{tab:arith_2cpl}.
When going from 2 bits to 3 bits, only the leftmost bit needs to be
copied (or sign extend).
copied (or sign extended).
In fact, this property holds true for every number of bits: we can always sign
extend existing representations when we increase the number of bits.
......@@ -418,7 +418,7 @@ The reference manual for \emph{fl} is available in \cite{VossII-manual}.
VossII is mainly developed by Carl Seger, and has been made open source in
February 2020.
A tool paper about VossII has been submitted to Memocode '20\cite{VossII}.
A tool paper about VossII has been submitted to Memocode '20 \cite{VossII}.
The whole CEPHALOPODE processor is written in \emph{fl}.
To see an example of how VossII works, look at the code in listing
......@@ -566,6 +566,7 @@ Using VossII, we could use the built in \texttt{Moore\_FSM} function to
describe the above FSM, as shown in listing \ref{fl:4ph}.
Moore_FSM "handshaker" clk state (reset --- IDLE) [
......@@ -603,12 +604,12 @@ To overcome these problems we had the idea to design Stately: a tool that
would let us design FSMs in visual mode and that would directly output
\emph{fl} code.
The tool itself was mainly developed by Jeremy Pope\cite{stately-git}, but Carl
The tool itself was mainly developed by Jeremy Pope \cite{stately-git}, but Carl
Seger and I provided most of the user feedback.
Moreover, most of the design ideas (like the virtual states we will discuss
in \ref{subsec:comparator}) came up during out meetings.
This is why the three of us are listed on the paper we submited for
Stately \cite{stately}.
\section[Designing the ALU]{Designing the Arithmetical and Logical Unit}
......@@ -688,7 +689,7 @@ This does not require a clock cycle, so it should not appear in the final FSM.
However, it is useful to visualize it in order to understand what the machine
is doing\footnote{This is not entirely obvious in this case, but will be
abundantly clear in the adder FSM in Fig.~\ref{fig:addsub_fsm}.}.
See~\cite{stately} for more details on these virtual states.
See~ \cite{stately} for more details on these virtual states.
The FSM is divided into three parts:
......@@ -1078,7 +1079,8 @@ This is not as obvious as it seems, because a unit such as the multiplier unit
The logical unit is by far the simplest one.
The four logical operators are only strict in their first argument:
In fact, because of lazy evaulation, we only need the first argument of each
operation to determine the result:
\item[NOT] it is self-evident for the negation;
\item[OR] in the case of \texttt{A OR B}, if \texttt{A} is
......@@ -1098,10 +1100,44 @@ is immediate after that.
\section{Further work}
There are three horizons towards which further work is required.
First, it would be great to have a first implementation of the division/modulus
unit and of the square root unit.
This could allow testing on “real” cases to be performed, and could give us a
first estimation of how power efficient our approach is.
Moreover, having a functional hardware means the rest of the Octopi team can
test their tools (like the assembler) directly on it.
Then, the power of VossII could be used to prove the hardware correct.
This is of course a major goal of the Octopi project.
Finally, more efficient hardware could be developed.
This more efficient hardware could be proved correct more easily, because all
the hard work would have been done with the simpler versions.
At this point, all the modules I presented are implemented and functional.
The addition/subtraction, logical, comparator and cleaning modules have been
tested and are presumably bug free.
These modules seem ready to be part of the first version of the CEPHALOPODE
Even though the internship happened under stressful conditions, I personnally
really enjoyed it.
I am not really interested in IoT, yet the project I worked on was very
Carl and Jeremy were very welcoming, and it was nice to work with them.
The project was well-suited for a five month internship.
It is accessible with the hardware formation we have (the “\emph{Digital
systems}” course), but is challenging nonetheless.
I strongly recommend other students to check this project for their next
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