Note that \emph{K} and \emph{I} create an \emph{indirection node} (represented
by the $=$ symbol), which is similar to a symbolic link in Linux.
These nodes ensure laziness is not lost \cite{Pey87}.
...
...
@@ -244,8 +244,7 @@ Consider this $\lambda$-expression:
\]
After compiling this to combinators using a standard “brackecting” approach
\cite{Pey87}, we would obtain the leftmost graph shown in figure
\ref{fig:gr_ex}.
\cite{Pey87}, we would obtain the leftmost graph shown in Fig~\ref{fig:gr_ex}.
\begin{figure}[ht]
\centering
...
...
@@ -281,7 +280,9 @@ The different types include:
next part of the integer. More details in \ref{subsubsec:api}.
\end{itemize}
Apart from indirection node which are handled directly by the memory controller, all nodes are decoded by the reduction engine and processed accordingly.
Apart from indirection node which are handled directly by the memory
controller, all nodes are decoded by the reduction engine and processed
accordingly.
When it detects the application of a primitive function to two or three
arguments, it sends the data to the ALU to be processed.
...
...
@@ -310,7 +311,7 @@ Suppose now that the initial design has a heater that
can change the temperature in the room by at most one degree per minute
and that all computations are performed with 8 bits 2's complement arithmetic.
With some effort, it is not too difficult to show that this IoT controlled
system will guarantee that the temperature never go above 33°C.
system will guarantee that the temperature never goes above 33°C.
Suppose now that the heater is replaced with a more efficient one that
can raise the temperature 3°C per minute.
...
...
@@ -420,7 +421,7 @@ February 2020.
A tool paper about VossII has been submitted to Memocode '20 \cite{VossII}.
The whole CEPHALOPODE processor is written in \emph{fl}.
To see an example of how VossII works, look at the code in listing
To see an example of how VossII works, look at the code in Listing
\ref{fl:andor}.
This code implements a part of the logical unit which will be described in
\ref{subsec:logical}.
...
...
@@ -460,16 +461,17 @@ let v_AO = STE_debug ckt_AO;
\end{listing}
As you can see, the syntax is fairly similar to a typical functional language.
The \texttt{ENUM} construction (as well as \texttt{TYPE} or \texttt{STRUCT})
As can be seen, the syntax is fairly similar to a typical functional language.
The \texttt{ENUM} constructor (as well as \texttt{TYPE} or \texttt{STRUCT})
allows the user to define a new hardware type, similar to what can be done in
C.
The first function features record types (with access to the field
\texttt{int} of the node \texttt{node\_Int\_false}).
For more complicated modules (such as \texttt{AND\_OR\_unit}), you first
declare the interface of the module before describing its content with
\texttt{CELL}, which takes a name and a list of \emph{wirings}.
For more complicated modules (such as \texttt{AND\_OR\_unit}), the interface of
the module is first described before the content is defined.
The content is defined with \texttt{CELL}, which takes a name and a list of
\emph{wirings}.
A \emph{wiring} can be either a direct affection (the wire \texttt{node\_out}
is directly connected to the output of the \texttt{IF THEN ELSE}
construct\footnote{This consctruct is in fact a multiplexer, as shown in
...
...
@@ -502,8 +504,8 @@ let shadok =
Finally, each circuit can be drawn with \texttt{STE\_debug} and shown to the
user.
In that case, calling \texttt{v\_AO} will result in the window on figure
\ref{fig:andor}.
In that case, calling \texttt{v\_AO} will result in the window in
Fig~\ref{fig:andor}.
\begin{figure}[ht]
\centering
...
...
@@ -525,9 +527,9 @@ to describe the different states a circuit will go through.
FSMs are in fact finite automata that read inputs from the rest of the circuit
and output a state name.
To showcase a concrete example, imagine some module wants to read data from
memory.
The process is the following:
To showcase a concrete example, imagine that some module wants to read data
from memory.
The process would be as follows:
\begin{enumerate}
\item[IDLE] At the begining, the reading module does nothing until prompted
by another module to do something.
...
...
@@ -548,10 +550,9 @@ The process is the following:
that the reading task has been completed.
\end{enumerate}
As you can see, this process is clearly divided into four steps with a clear
condition to go from one step to another: this process can be represented by a
FSM.
Such a FSM is shown on figure \ref{fig:4ph}.
This process is divided into four distinct steps with a clear condition to go
from one step to another: this process can be represented by a FSM.
Such a FSM is shown in Fig~\ref{fig:4ph}.
For more details on 4 phase handshake protocols, see \cite{category}.
\begin{figure}[ht]
...
...
@@ -562,7 +563,7 @@ For more details on 4 phase handshake protocols, see \cite{category}.
\end{figure}
Using VossII, we could use the built in \texttt{Moore\_FSM} function to
describe the above FSM, as shown in listing \ref{fl:4ph}.
describe the above FSM, as shown in Listing \ref{fl:4ph}.
