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Martin Pepin
sysdig
Commits
827d3872
Commit
827d3872
authored
Jan 14, 2017
by
Martin Pépin
Browse files
Handle mult in ALU
parent
7572219c
Changes
2
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cpu/src/alu/main.mj
View file @
827d3872
require registers
require alu/utils
(* The ALU implementation
shamt et constantes sont envoyés par le multiplexeur
...
...
@@ -7,43 +8,62 @@ require alu/utils
*)
ALU(input1:[32], input2:[32], alu_control:[4]) = (alu_zero, result:[32]) where
result =
result
_aux
=
mux_n<word>(alu_control[0], (* if 1 then shift or HI/Lo, else logical or artih*)
(* 1... *)
mux_n<word>(alu_control[2], (* if 1 then HI/LO, else logical shift *)
mux_n<word>(alu_control[3], (* Case HI/LO *)
read_HI(), (*TODO*)
read_LO()
), (*TODO*)
(* 1.1. *)
zero_n<word>(), (* HI/LO *)
(* 1.0. *)
mux_n<word>(alu_control[1], (* Case logical shift *)
(* 110. *)
shift_by_reg_ALU(input1, input2, 1, alu_control[3]),
(* 100. *)
shift_by_reg_ALU(input1, input2, 0, 0)
)
),
mux_n<word>(alu_control[1], (*if 1 then logical else arihtmetical *)
(* 0*** *)
mux_n<word>(alu_control[1], (* if 1 then logical else arihtmetical *)
(* 01.. *)
mux_n<word>(alu_control[2],
(* 011. *)
mux_n<word>(alu_control[3],
xor_ALU(input1, input2),
nor_ALU(input1, input2)
),
(* 010. *)
mux_n<word>(alu_control[3],
(* 0101 *)
or_ALU(input1, input2),
(* 0100 *)
and_ALU(input1, input2)
)
),
(* 00.. *)
mux_n<word>(alu_control[2],
mux_n<word>(alu_control[3],
(*TODO : multiplication et division*)
zero_n<32>(),
zero_n<32>()
),
(* 001. *)
zero_n<word>(), (* mult/div *)
add_ALU(input1, input2, alu_control[3])
(* 000. *)
add_ALU(input1, input2, alu_control[3])
)
)
);
(* Signal pour les branchements *)
alu_zero = equal_zero_n<32>(result);
(* Traitement de la multiplication *)
write_hilo = equal_n<3>(0.0.1, alu_control[..2]);
read_hilo = alu_control[0] & alu_control[2];
result_mul = mul_n<word,word>(input1, input2, zero_n<word-1>());
hi_val = HI<word>(result_mul[..31], write_hilo & alu_control[3]);
lo_val = LO<word>(result_mul[32..], write_hilo & not(alu_control[3]));
result = mux_n<word>(
not read_hilo,
result_aux,
mux_n<word>(alu_control[3], hi_val, lo_val)
);
end where
cpu/src/main.mj
View file @
827d3872
...
...
@@ -33,12 +33,10 @@ main (b) = (instruction:[word], syscall, ctrl:[2]) where
imm = extand_const_n<16,16>(instruction[16..31]);
alu_input_2 = mux_n<word>(
use_shamt,
extand_left_n<5,word-5>(instruction[21..25]),
extand_left_n<5,word-5>(instruction[21..25]
, 0
),
mux_n<word>(alu_src, imm, read_data2)
);
(alu_zero, alu_result) = ALU<word>(read_data1,
alu_input_2,
alu_ctrl);
(alu_zero, alu_result) = ALU(read_data1, alu_input_2, alu_ctrl);
(* Reading/writing RAM *)
read_data_mem = data_mem<32,word>(alu_result, read_data2, mem_read,
...
...
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