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Martin Pepin
sysdig
Commits
d3e914b5
Commit
d3e914b5
authored
Jan 14, 2017
by
Martin Pépin
Browse files
Merge branch 'master' of git.eleves.ens.fr:mpepin/sysdig
parents
8d276101
a3c6ca29
Changes
1
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cpu/src/alu/main.mj
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d3e914b5
require registers
require
ALU
/utils
require
alu
/utils
(* The ALU implementation
TODO
shamt et constantes sont envoyés par le multiplexeur
*)
ALU(input1:[32], input2:[32], alu_control:[4],
alu_op:[3],
use_shamt
,
shamt:[5], constant:[16]) =
(alu_zero, result:[32]) where
ALU(input1:[32], input2:[32], alu_control:[4], use_shamt
) =
(alu_zero, result:[32]) where
R_format = equal_zero_n<3>(alu_op);
result =
mux(R_format,
mux(alu_control[0], (* if 1 then shift or HI/Lo, else logical or artih*)
mux(alu_control[2], (* if 1 then HI/LO, else logical shift *)
mux(alu_control[3], (* Case HI/LO *)
...
...
@@ -18,18 +17,11 @@ ALU(input1:[32], input2:[32], alu_control:[4], alu_op:[3], use_shamt,
read_LO()
), (*TODO*)
mux(alu_control[1], (* Case logical shift *) (*TODO : optimiser use_shamt ?*)
mux(use_shamt,
shift_by_shamt_ALU(input1, shamt, 1, alu_control[3]),
shift_by_reg_ALU(input1, input2, 1, alu_control[3])
),
mux(use_shamt, (* Case logical shift left *)
shift_by_shamt_ALU(input1, shamt, 0, 0),
shift_by_reg_ALU(input1, input2, 0, 0)
mux(alu_control[1], (* Case logical shift *)
shift_by_reg_ALU(input1, input2, 1, alu_control[3]),
shift_by_reg_ALU(input1, input2, 0, 0)
)
)
),
),
mux(alu_control[1], (*if 1 then logical else arihtmetical *)
mux(alu_control[2],
...
...
@@ -54,10 +46,6 @@ ALU(input1:[32], input2:[32], alu_control:[4], alu_op:[3], use_shamt,
add_ALU(input1, input2, alu_control[3]),
)
)
),
(*TODO : opérations pas format R *)
zero_n<32>()
);
);
alu_zero = equal_zero_n<32>(result);
end where
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